3. Multiple Drivers

• The goal is to connect both inputs a and b to the same output y using two separate continuous assignments.
• In Verilog, multiple continuous assignments to the same wire create multiple drivers.
• When both inputs have the same value, the output y will reflect that value.
• When the inputs differ, the output becomes unknown (x) because of the conflict.
• This demonstrates how Verilog models contention when different signals try to drive the same net.

module top_module( input a,output y,input b );
    assign y=a;
    assign y=b;
endmodule