NOT Gate

October 15, 2025

Solving Approach

How do you plan to solve?

the given question clearly explains the logic gate (not)is used here and the ouput should always be the inverse of the input signal

EX: a=1/Y=0 for not gate

Code

module top_module(input a ,output y);
assign y = ~ a;
endmodule

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Testbench Code

`timescale 1ns/1ps

module tb;
  // Inputs
  reg a;
  // Outputs
  wire y;
  // Expected Outputs
  reg expected_y;

  // Mismatch signal
  wire mismatch = (y !== expected_y);

  // DUT
  top_module dut(.a(a), .y(y));

  integer TOTAL, PASS, FAIL;
  initial begin
    $dumpfile("tb.vcd");
    // Dump inputs, outputs, expected, and mismatch
    $dumpvars(0, tb.a, tb.y, tb.expected_y, tb.mismatch);

    TOTAL=0; PASS=0; FAIL=0;

    a=0; expected_y=1; #5;
    TOTAL++; if (!mismatch) PASS++; else FAIL++;
    $display("a=%b | y=%b | expected_y=%b | mismatch=%b",
              a, y, expected_y, mismatch);

    a=1; expected_y=0; #5;
    TOTAL++; if (!mismatch) PASS++; else FAIL++;
    $display("a=%b | y=%b | expected_y=%b | mismatch=%b",
              a, y, expected_y, mismatch);

    $display("======================================");
    $display("TOTAL_TEST_CASES=%0d", TOTAL);
    $display("TOTAL_PASSED_TEST_CASES=%0d", PASS);
    $display("TOTAL_FAILED_TEST_CASES=%0d", FAIL);
    $display("ALL_TEST_CASES_PASSED=%s", (FAIL==0) ? "true" : "false");
    $display("======================================");
    $finish;
  end
endmodule