EWskill Home
Verilog
Prev Problem
Next Problem
Login
Verilog
Close menu
Loading...
Task
Discussion
Submissions
Solution
Report
4. NOT Gate
All Submissions
Back To All Submissions
Previous Submission
Next Submission
kirubakaranJ
October 14, 2025
Solving Approach
How do you plan to solve it?
Code
module top_module( input a, output y ); assign y= ~a; endmodule
Was this helpful?
0
Upvote
Downvote