89. Serial-In Parallel-Out Register

Design a 4-bit SIPO register that shifts a serial input stream MSB-first. On each rising edge of CLK, the new bit is inserted into Q[3] and the existing bits shift right.

Requirements

• Module: sipo4
• Ports:
  • Inputs:
    • CLK
    • RST
    • serial_in
  • Outputs:
    • Q[3:0]
• Functional behavior
  • Asynchronous active-high reset: RST=1 → Q=4'b0000.
  • On posedge CLK with RST=0: Q <= {serial_in, Q[3:1]} (MSB-first).

Example

Starting from Q=0000, applying serial bits 1,0,1,1 on consecutive rising edges produces:

• After 1st edge: Q=1000
• After 2nd edge: Q=0100
• After 3rd edge: Q=1010
• After 4th edge: Q=1101