88. Parallel-In Serial-Out Register

How do you plan to solve it?

module piso4 (
    input        CLK,
    input        RST,
    input        LOAD,
    input  [3:0] D,
    output reg   serial_out
);
reg [3:0]sr;
always @(posedge RST)begin
   if(RST) begin
        sr<=0;
        serial_out<=0;
   end
end
always @ (posedge CLK or posedge RST) begin
    if(RST == 0) begin
        if(LOAD) begin
            sr<=D;
        end else begin
            serial_out<=sr[0];
            sr={1'b0,sr[3:1]};
        end
    end
end
endmodule