88. Parallel-In Serial-Out Register

How do you plan to solve it?

module piso4 (
    input        CLK,
    input        RST,
    input        LOAD,
    input  [3:0] D,
    output reg   serial_out
);
    // Write your code here
    reg [3:0]data;
    always@(posedge CLK,posedge RST)begin
        if(RST)begin
            data <= 4'd0;
            serial_out <= 1'b0;
        end
        else begin
            if(LOAD)
              data <= D;
            else begin
                data <= {1'b0,data[3:1]};
                serial_out <= data[0];
            end
        end
    end
    
endmodule