88. Parallel-In Serial-Out Register

How do you plan to solve it?

module piso4 (
    input        CLK,
    input        RST,
    input        LOAD,
    input  [3:0] D,
    output reg   serial_out
);
    // Write your code here
    reg [3:0]SR;

    always@(posedge CLK or posedge RST)begin
        
        if(RST)begin
            serial_out <= 1'b0;
            SR         <= 4'b0000;
        end
        else if(LOAD)begin
            SR <= D;
        end 
         else if(~LOAD) begin
            serial_out <= SR[0];
            SR <= {1'b0,SR[3:1]};
        end
        
    end
endmodule