88. Parallel-In Serial-Out Register

How do you plan to solve it?

module piso4 (
    input        CLK,
    input        RST,
    input        LOAD,
    input  [3:0] D,
    output reg  serial_out
);
reg[3:0] pipo;
    // Write your code here
    always@(posedge CLK or posedge RST)begin
    if(RST) begin pipo<=4'd0;
    serial_out<=1'b0;
    end
    else if(LOAD) pipo<=D;
    else begin
        pipo<=(pipo>>1);
        serial_out<=pipo[0];
    end
    end
    //assign serial_out=pipo[0];
endmodule