88. Parallel-In Serial-Out Register

How do you plan to solve it?

module piso4 (
    input        CLK,
    input        RST,
    input        LOAD,
    input  [3:0] D,
    output reg   serial_out
);
    // Write your code here
    reg [3:0] Q;
    always @(posedge CLK or posedge RST) begin 
        if(RST) begin Q<=4'h0; serial_out<=1'b0; end
        else if(LOAD) Q<=D;
        else begin serial_out<=Q[0]; Q<={1'b0,Q[3:1]}; end
    end
endmodule