88. Parallel-In Serial-Out Register

How do you plan to solve it?

module piso4 (
    input        CLK,
    input        RST,
    input        LOAD,
    input  [3:0] D,
    output reg   serial_out
);

reg [3:0] SR;

always @(posedge CLK or posedge RST) begin
    if (RST) begin
        serial_out <= 1'b0;
        SR <= 4'd0;
    end else if (LOAD) begin
        SR <= D;
    end else begin
        {SR, serial_out} <= {1'b0, SR};
    end
end
endmodule