88. Parallel-In Serial-Out Register

How do you plan to solve it?

module piso4 (
    input        CLK,
    input        RST,
    input        LOAD,
    input  [3:0] D,
    output reg   serial_out
);
    // Write your code here
    reg [3:0]s;

    always@(posedge CLK)
    begin
        if(RST)
        begin
        s<=4'd0;
        serial_out<=0;
        end
        else if(LOAD)
        s<=D;
        else
        begin
        serial_out <= s[0]; 
        s <= {1'b0, s[3:1]};
        end

    end
    
endmodule