88. Parallel-In Serial-Out Register

How do you plan to solve it?

module piso4 (
    input        CLK,
    input        RST,
    input        LOAD,
    input  [3:0] D,
    output reg   serial_out
);
    // Write your code here
    reg [3:0] d;
    always@(posedge CLK)
    begin
        if(RST)
        begin
            d <= 1'b0;
            serial_out <= 1'b0;
        end
        else if(LOAD)
        begin
            d <= D;
        end
        else
        begin
            d <= {1'b0, d[3:1]};
            serial_out <= d[0];
        end
        //serial_out <= d[0];
    end
    
endmodule