88. Parallel-In Serial-Out Register

How do you plan to solve it?

module piso4 (
    input        CLK,
    input        RST,
    input        LOAD,
    input  [3:0] D,
    output reg   serial_out
);
    reg [3:0] sr_int;
    // Write your code here
    always@(posedge CLK, RST) begin
        if(RST) begin
            serial_out <= 1'b0;
            sr_int <= 4'b0;
        end else begin
            if(LOAD) begin
                sr_int <= D;
            end else begin
                serial_out <= sr_int[0];
                sr_int <= {1'b0, sr_int[3:1]};
            end
        end

    end
    
endmodule