88. Parallel-In Serial-Out Register

How do you plan to solve it?

module piso4 (
    input        CLK,
    input        RST,
    input        LOAD,
    input  [3:0] D,
    output reg   serial_out
);
    // Write your code here
    reg [3:0] ds;
    always @(posedge CLK or posedge RST) begin 
        if(RST) begin serial_out <= 0; ds <= 0; end
        else if(LOAD) ds <= D;
        else begin
            serial_out <= ds[0];
            ds <= {1'b0,ds[3:1]};
        end 
    end
endmodule