88. Parallel-In Serial-Out Register

How do you plan to solve it?

module piso4 (
    input        CLK,
    input        RST,
    input        LOAD,
    input  [3:0] D,
    output reg   serial_out
);
    // Write your code here
    reg [3:0]shift;
  always@(posedge CLK or posedge RST)begin
  if(RST)begin
  serial_out<=4'b0;
  shift<=1'b0;end
  else if(LOAD)begin
    shift<=D;
  serial_out<=serial_out;
  end else begin
    serial_out<=shift[0];
    shift<={1'b0, shift[3:1]};
  end
  end

endmodule