88. Parallel-In Serial-Out Register

How do you plan to solve it?

module piso4 (
    input        CLK,
    input        RST,
    input        LOAD,
    input  [3:0] D,
    output reg   serial_out
);
 reg [3:0]SR;
 always @ (posedge CLK or posedge RST )begin
    if (RST) begin
      SR <= 4'b0000;
      serial_out=1'b0;
    end
    else
       if (LOAD)begin
         SR <= D;
         serial_out <= serial_out;
       end

       else begin
         SR <= {1'b0,SR[3:1]};
         serial_out <= SR[0];
       end
 end

          
          
           // Write your code here
    
endmodule