88. Parallel-In Serial-Out Register

How do you plan to solve it?

module piso4 (
    input        CLK,
    input        RST,
    input        LOAD,
    input  [3:0] D,
    output reg   serial_out
);
    // Write your code here
    reg [3:0] sr;
    always @(posedge CLK) begin
        if(RST) begin
            sr <= 4'b0000;
            serial_out <= 4'b0000;
        end

        else if(LOAD==1) begin
            sr <= D;
            serial_out <= serial_out;
        end
        else if (!LOAD) begin
            serial_out <= sr[0];
            sr <={1'b0,sr[3:1]};
        end

    end
    
endmodule