88. Parallel-In Serial-Out Register

How do you plan to solve it?

module piso4 (
    input        CLK,
    input        RST,
    input        LOAD,
    input  [3:0] D,
    output reg   serial_out
);
    // Write your code here
    reg [3:0]SR;
    always @(posedge CLK or posedge RST or posedge LOAD) begin
        if (RST) begin 
            SR <= 4'b0; 
            serial_out = 1'b0;
        end

        else if (LOAD) SR <= D;
        else begin
            
            serial_out <= SR[0];

            SR <= {1'b0, SR[3:1]};

        end

    end
endmodule