88. Parallel-In Serial-Out Register

How do you plan to solve it?

module piso4 (
    input        CLK,
    input        RST,
    input        LOAD,
    input  [3:0] D,
    output reg   serial_out
);
    // Write your code here
     reg [3:0]SR;
    always @(posedge CLK) begin
       
        if(RST==1) begin
            SR<=0;
            serial_out<=0;
            end
        else begin
            if(LOAD==1) begin
               SR<=D;
                serial_out<=serial_out;
            end
            else begin
                serial_out<=SR[0];
                SR<={1'b0,SR[3:1]};
            end
        end

    end
endmodule