88. Parallel-In Serial-Out Register

How do you plan to solve it?

module piso4 (
    input        CLK,
    input        RST,
    input        LOAD,
    input  [3:0] D,
    output reg   serial_out
);
    reg [3:0] SR;  // Internal shift register

    // Asynchronous reset, synchronous load and shift
    always @(posedge CLK or posedge RST) begin
        if (RST) begin
            SR <= 4'b0000; 
            serial_out <= 1'b0;
        end else begin
            if (LOAD) begin 
                SR <= D;  // Load parallel data, do NOT output LSB yet
            end else begin
                serial_out <= SR[0];  // Output LSB
                SR <= {1'b0, SR[3:1]};  // Shift right, zero-fill from left
            end
        end
    end
endmodule