88. Parallel-In Serial-Out Register

How do you plan to solve it?

module piso4 (
    input        CLK,
    input        RST,
    input        LOAD,
    input  [3:0] D,
    output reg   serial_out
);

reg [3:0] Sr;
    // Write your code here
    always @(posedge CLK) begin
        if(RST) begin
            Sr<=0;
            serial_out<=0;
        end
        else if(LOAD) begin
            Sr<=D;
            serial_out<=serial_out;
        end
        else begin
            serial_out<=Sr[0];
            Sr={1'b0,Sr[3:1]};
            
        end
    end
        


endmodule