88. Parallel-In Serial-Out Register

How do you plan to solve it?

module piso4 (
    input        CLK,
    input        RST,
    input        LOAD,
    input  [3:0] D,
    output reg   serial_out
);
    // Write your code here
    reg [3:0] SR;
    always @(posedge CLK or posedge RST )   begin 
        if(RST ==1'b1)  begin 
        SR<=4'b0000;
        serial_out<=1'b0;
        end
        else  begin 
            if(LOAD==1'b1)
            SR<=D;
            else begin 
                serial_out<=SR[0];
                SR<=SR/2'b10;
            end
        end
    end

    
endmodule