88. Parallel-In Serial-Out Register

How do you plan to solve it?

module piso4 (
    input        CLK,
    input        RST,
    input        LOAD,
    input  [3:0] D,
    output reg   serial_out
);
    reg [3:0] Q;
    // Write your code here
    always@(posedge CLK, posedge RST)
    begin
        if(RST==1)
        begin
            serial_out=1'b0;
            Q<=4'd0;      
        end
        else
        begin
            if(LOAD==1)
            begin
                Q<=D;
            end
            else
            begin   
                serial_out<=Q[0];
                Q<={1'd0,Q[3:1]};
            end
        end
    end
endmodule