88. Parallel-In Serial-Out Register

How do you plan to solve it?

module piso4 (
    input        CLK,
    input        RST,
    input        LOAD,
    input  [3:0] D,
    output reg   serial_out
);
    reg [3:0] out;
    always@(posedge CLK)begin
        if(RST) begin
            serial_out <= 0;
            out <= 0;
        end
        else begin 
            if(LOAD) out <= D;
            else begin 
                serial_out <= out[0];
                out <= {1'b0,out[3:1]};
            end
        end
    end
    
endmodule