88. Parallel-In Serial-Out Register

How do you plan to solve it?

a PISO shift register

module piso4 (
    input        CLK,
    input        RST,
    input        LOAD,
    input  [3:0] D,
    output reg   serial_out
);
    // Write your code here
    reg [3:0] Q;
    always @(posedge CLK or posedge RST) begin
        if(RST) begin
            Q <= 4'd0;
            serial_out <= 1'b0;
        end
        else begin
            if (LOAD)
                Q <= D;
            else begin
                serial_out <= Q[0];
                Q <= Q >> 1'b1;
            end
        end
    end

    
endmodule