88. Parallel-In Serial-Out Register

How do you plan to solve it?

module piso4 (
    input        CLK,
    input        RST,
    input        LOAD,
    input  [3:0] D,
    output reg   serial_out
);
    // Write your code here
    reg [3:0] register;
    always@(posedge CLK or posedge RST) 
    if (RST) begin
    register <= 0;
    serial_out <= 0;
    end else begin
    if (LOAD == 1) begin
        register <= D;
    end else begin
        serial_out <= register[0];
        register <= {1'b0,register[3:1]};
        

    end;
    end;
    
endmodule