88. Parallel-In Serial-Out Register

How do you plan to solve it?

module piso4 (
    input        CLK,
    input        RST,
    input        LOAD,
    input  [3:0] D,
    output reg   serial_out
);
    reg [3:0] internal_SR;

    always @(posedge CLK or posedge RST) begin
        if (RST) begin              // Reset
            internal_SR <= 4'b0000;
            serial_out <= 1'b0;
        end else if (LOAD) begin    // Load
            internal_SR <= D;
        end else begin              // Shift
            serial_out <= internal_SR[0];
            internal_SR <= { 1'b0, internal_SR[3:1] };
        end
    end

endmodule