88. Parallel-In Serial-Out Register

How do you plan to solve it?

module piso4 (
    input        CLK,
    input        RST,
    input        LOAD,
    input  [3:0] D,
    output reg   serial_out
);
    // Write your code here
    reg [3:0] int_reg; 
    always @( posedge CLK , posedge LOAD )
    begin
        if( RST )
        begin
            serial_out  <= 1'b0;
            int_reg     <= 4'd0;
        end
        else begin
            if( LOAD )
            begin
                int_reg <= D;
            end
            else
            begin
                serial_out  <= int_reg[0];
                int_reg     <= { 1'b0, int_reg[3:1]};
            end
        end
    end
endmodule