88. Parallel-In Serial-Out Register

How do you plan to solve it?

module piso4 (
    input        CLK,
    input        RST,
    input        LOAD,
    input  [3:0] D,
    output reg   serial_out
);
    // Write your code here
    reg [3:0] shift_reg;
    always @(posedge CLK) begin
        if(RST) begin
            serial_out<=1'b0;
            shift_reg<=4'b0000;
        end
        else if(LOAD) begin
            shift_reg<=D;
            serial_out<=serial_out;
        end
        else begin
            serial_out<=shift_reg[0];
            shift_reg<={1'b0,shift_reg[3:1]};
        end
    end

    
endmodule