88. Parallel-In Serial-Out Register

How do you plan to solve it?

module piso4 (
    input        CLK,
    input        RST,
    input        LOAD,
    input  [3:0] D,
    output reg   serial_out
);
    reg [3:0] shift_reg;

    always @(posedge CLK or posedge RST) begin
        if (RST)
            shift_reg  <= 4'b0000;
        else if (LOAD)
            shift_reg  <= D;
        else 
            serial_out <= shift_reg[0];         // emit LSB
    end
    always @(posedge CLK or posedge RST) begin
        if (RST) 
            serial_out <= 1'b0;
        else if (LOAD)
            serial_out <= serial_out;           // hold output on load edge
        else 
            shift_reg  <= {1'b0, shift_reg[3:1]};
    end
endmodule