88. Parallel-In Serial-Out Register

How do you plan to solve it?

module piso4 (
    input        CLK,
    input        RST,
    input        LOAD,
    input  [3:0] D,
    output reg   serial_out
);
    reg [3:0] temp;
    always @(posedge CLK) begin
        if (RST) begin
            serial_out <= 4'b0000;
            temp <= 4'b0000;
        end else if (LOAD) begin
            temp <= D;
        end else if (LOAD == 0) begin
            //shift_right
            temp <= {1'b0, temp[3:1]}; 
            serial_out <= temp[0];
        end
    end 
    
endmodule