88. Parallel-In Serial-Out Register

How do you plan to solve it?

module piso4 (
    input        CLK,
    input        RST,
    input        LOAD,
    input  [3:0] D,
    output reg   serial_out
);
    // Write your code here
    
    reg [3:0] Q;

    always @ (posedge CLK or posedge RST) begin
        
        if(RST) begin 
            Q <=0;
            serial_out <= 0;
        end else begin
            if(LOAD) Q <= D;
            else begin
                {Q , serial_out} = {1'b0 , Q};
            end
        end
    end

endmodule