88. Parallel-In Serial-Out Register

How do you plan to solve it?

module piso4 (
    input        CLK,
    input        RST,
    input        LOAD,
    input  [3:0] D,
    output reg   serial_out
);
    // Write your code here
    reg[3:0] piso;
    always@(posedge CLK or negedge RST)
    begin
        if(RST)
        begin
            piso<= 4'd0;
            serial_out<=1'd0;
        end
        else
        begin
            if(LOAD==1)
            piso<=D;
            else
            begin
            serial_out<=piso[0];
            piso<= piso>>1;
            end
            
        end
    end
    
endmodule