84. T Flip-Flop with Asynchronous Preset and Reset

module t_ff_async_pr (
    input  CLK,
    input  RST,
    input  PRE,
    input  T,
    output reg Q
);
    always @(posedge CLK or posedge RST or posedge PRE) begin
        if (RST)
            Q <= 1'b0;
        else if (PRE)
            Q <= 1'b1;
        else if (T)
            Q <= ~Q;
        else
            Q <= Q;
    end
endmodule

💡Remember

• List all asynchronous controls in the sensitivity list and encode clear priority (RST over PRE).
• While an async control is asserted, clock edges do not change Q; release cleanly in real hardware.
• Nonblocking (<=) ensures toggles use the pre-edge value of Q and avoids races.