84. T Flip-Flop with Asynchronous Preset and Reset

Design a positive-edge–triggered T flip-flop with active-high asynchronous reset and preset. Reset dominates preset; preset forces Q=1 only when reset is inactive.

Requirements

• Module: t_ff_async_pr
• Ports:
  • Inputs:
    • CLK
    • RST
    • PRE
    • T
  • Outputs:
    • Q
• Functional behavior (priority)
  • RST=1 → Q=0 immediately.
  • else PRE=1 → Q=1 immediately.
  • else on posedge CLK:
    • T=1 → Q=~Q
    • T=0 → hold
• Modeling constraints
  • Use always @() with nonblocking assignments (<=).
  • Encode priority: RST > PRE > toggle/hold.

Behaviour / Worked Example

From Q=0:

1. PRE↑ (with RST=0) → Q=1
2. RST↑ → Q=0 (reset dominates)
3. RST=0, PRE=0, T=1 at edge → Q=1 (toggle)
4. T=0 at edge → Q=1 (hold)