83. T Flip-Flop

module t_ff (
    input  CLK,
    input  T,
    output reg Q
);
    always @(posedge CLK) begin
        if (T)
            Q <= ~Q;
        else
            Q <= Q;
    end
endmodule

💡Remember

• A T flip-flop without reset powers up unknown; in simulation a pure toggle/hold machine can remain X forever unless seeded.
• Nonblocking (<=) ensures the toggle uses the pre-edge value of Q and avoids races.