11. Vector Concatenation

How do you plan to solve it?

/*Write your code here*/

module concat8_packer(
    input [3:0] A,
    input [1:0] B,
    input C, D,
    output [7:0] OUT 
);

    wire not_C;
    assign not_C = ~C;

    assign OUT = {A[3:0],B[1:0],not_C,D};

endmodule