1. Wire

Solution by explicitly declaring a wire

module top_module(input a, output y);
  // Pass-through using a net and continuous assignment
  wire w;
  assign w = a;
  assign y = w;
endmodule

Minimal, idiomatic & identical solution with no logic or hardware differences:

module top_module (
    input  a,
    output y
);
    assign y = a;
endmodule

💡Remember

Both solutions describe the same hardware: input a directly connected to output y.
Declaring an extra wire (Solution 1) is pedagogical — useful for beginners to see signal flow step by step.
The minimal form (Solution 2) is idiomatic Verilog — concise, clean, and preferred in practice.
Continuous assignments (assign) on wires always imply combinational connectivity without delay or storage.