1. Wire

Solution by explicitly declaring a wire
module top_module(input a, output y);
  // Pass-through using a net and continuous assignment
  wire w;
  assign w = a;
  assign y = w;
endmoduleMinimal, idiomatic & identical solution with no logic or hardware differences:
module top_module (
    input  a,
    output y
);
    assign y = a;
endmodule
💡Remember
Both solutions describe the same hardware: input a directly connected to output y.
Declaring an extra wire (Solution 1) is pedagogical — useful for beginners to see signal flow step by step.
The minimal form (Solution 2) is idiomatic Verilog — concise, clean, and preferred in practice.
Continuous assignments (assign) on wires always imply combinational connectivity without delay or storage.

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Testbench Code

`timescale 1ns/1ps

module tb;
  // Input
  reg a;
  // Output
  wire y;
  // Expected
  reg expected_y;

  // DUT
  top_module dut(.a(a), .y(y));

  // Mismatch (case-inequality handles X/Z correctly)
  wire mismatch = (y !== expected_y);

  integer TOTAL, PASS, FAIL;

  // Apply a value, derive expected, wait, update counters and print
  task apply_and_check;
    input a_val; // 1-bit, 4-state
    begin
      a = a_val;
      expected_y = a_val;   // pass-through golden: y should equal a (0/1/X/Z)
      #5;
      TOTAL = TOTAL + 1;
      if (!mismatch) PASS = PASS + 1; else FAIL = FAIL + 1;
      $display("a=%b | y=%b | expected_y=%b | mismatch=%b", a, y, expected_y, mismatch);
    end
  endtask

  initial begin
    $dumpfile("tb.vcd");
    // dump only input, output, expected, mismatch
    $dumpvars(0, tb.a, tb.y, tb.expected_y, tb.mismatch);

    TOTAL = 0; PASS = 0; FAIL = 0;

    // Tests: 0, 1, X, Z
    apply_and_check(1'b0);
    apply_and_check(1'b1);
    apply_and_check(1'bx);
    apply_and_check(1'bz);

    // Summary
    $display("TOTAL_TEST_CASES=%0d", TOTAL);
    $display("TOTAL_PASSED_TEST_CASES=%0d", PASS);
    $display("TOTAL_FAILED_TEST_CASES=%0d", FAIL);
    $display("ALL_TEST_CASES_PASSED=%s", (FAIL==0) ? "true" : "false");
    $finish;
  end
endmodule