1. Wire

How do you plan to solve it?

wire is a continuously driven data type in Verilog. It can be continuously driven by any other wire or a constant value (both constants and expressions) by using assign statement.

assign y = a; makes the output wire y be driven by the input wire a;
Thus whatever is the value of a will be the value of y.

module top_module(input a, output y);
  // Write your code here
  assign y = a;
endmodule