Latches and Flip-Flops Quick Reference Guide

A sequential circuit is a digital circuit whose output depends on:

• Current input
• Previously stored value

Unlike a combinational circuit, it can remember past information.

General relation:

Next State = Function of Present-State Inputs and Previous-State Inputs

1-Bit Memory Cell - A 1-bit memory cell stores one binary value: either 0 or 1.

An SR latch is a basic 1-bit memory cell with two inputs Set (S) and Reset (R).

It has two outputs: Q (Stored Output) and ~Q (Inverted Output)

Note: Q ≠ ~Q.

Fig. 1: SR Latch using two NAND and two NOT Gates

Table 1: SR Latch Truth Table and Logic Flow

Logic Flow

Set: S = 1, R = 0

• NOT1 produces 0.
• A 0 at NAND1 forces Q = 1.
• Q = 1 and NOT2 = 1 make ~Q = 0.

Reset: S = 0, R = 1

• NOT2 produces 0.
• A 0 at NAND2 forces ~Q = 1.
• ~Q = 1 and NOT1 = 1 make Q = 0.

Hold: S = 0, R = 0

Both NOT outputs are 1. The feedback keeps the previously stored value.

Invalid: S = 1, R = 1

Both NOT outputs become 0, forcing both NAND outputs HIGH. Therefore, Q and ~Q are no longer opposite.

Purpose

The ENABLE input controls when an SR latch is allowed to respond to S and R.

A clock signal can be connected to ENABLE:

• EN = 0: Input changes are blocked.
• EN = 1: Input changes are accepted.

Enabled SR Latch

The inputs are first combined with ENABLE:

Sg = S · EN
Rg = R · EN

These signals are then applied to the SR latch.

Another 2 NAND Gates are used for S and R with common input EN.

Fig. 2: SR Latch circuit using NAND with ENABLE input

Working

When EN = 0

Sg = 0 and Rg = 0 for all input combinations. The latch holds its previous value.

When EN = 1

Sg = S and Rg = R. The latch performs Set, Reset, Hold, or Invalid operation.

Table 2: Enabled SR Latch Truth Table

“X” means the input value does not matter.

Purpose

The JK latch improves the SR latch by removing the invalid input combination.

• J works like Set.
• K works like Reset.
• When J = K = 1, the stored output toggles.

Fig. 3: JK Latch circuit using NAND Gate

Advantages Over SR Latch

• The combination J = K = 1 is valid.
• It can toggle the stored output.
• It is useful in counters and switching circuits.

Table 3: JK Latch Truth Table

Race-Around Condition

Race-around occurs when:

• J = K = 1
• The latch is enabled for too long
• Output feedback remains active during the enabled period

When Q toggles, its new value is fed back to the input gates. If ENABLE is still active, the output toggles again. This can happen several times during one clock pulse.

The final output becomes uncertain.

Solutions

• Use a shorter clock pulse.
• Use edge-triggered operation.
• Use a master-slave arrangement.

Table 4: Latch and Flip-Flop Comparison

Level and Edge Activation

Table 5: Activation Types

	Active-HIGH or Positive	Active-LOW or Negative
Level-triggered	Definition: Active while the signal is HIGH. Working: The output can change while EN = 1. Notation: EN input without a bubble.	Definition: Active while the signal is LOW. Working: The output can change while EN = 0. Notation: EN input with a bubble.
Edge-triggered	Definition: Active only during a rising edge. Working: The output changes at  0 → 1. Notation: > without a bubble.	Definition: Active only during a falling edge. Working: The output changes at  1 → 0. Notation: > with a bubble.

D and T flip-flops use only one main input. They can be created using a JK flip-flop.

D Flip-Flop Using JK

Definition

A D or Data flip-flop stores the value available at input D during the active clock edge.

Its next output is:

Q(next) = D

Connections

J = D
K = ~D

Fig. 4: D Flip Flop using JK Flip Flop

Working

When D = 0

• J = 0
• K = 1
• The JK device performs Reset.
• Q(next) = 0

When D = 1

• J = 1
• K = 0
• The JK device performs Set.
• Q(next) = 1

Table 6: D Flip-Flop Truth Table

T Flip-Flop Using JK

Definition

A T or Toggle flip-flop changes its output when T = 1.

Its next output is:

Q(next) = T ⊕ Q

Connections

J = T
K = T

Fig. 5: T Flip Flop using JK Flip Flop

Working

When T = 0

• J = 0
• K = 0
• The JK device performs Hold.
• The output does not change.

When T = 1

• J = 1
• K = 1
• The JK device performs Toggle.
• The output changes to its opposite value.

Table 7: T Flip-Flop Truth Table

D Flip Flop and T Flip Flop Comparison

Table 8: D and T Flip-Flop Comparison

Basic Idea

An excitation table gives the input required to move from the present output to a required next output.

For example, it answers:

“What input should be applied to change Q = 0 into Q(next) = 1?”

Truth Table vs Excitation Table

• A truth table finds the next output from the inputs.
• An excitation table finds the required inputs from the desired output change.

Uses

Excitation tables are used for:

• Counter design
• State-machine design
• Sequential circuit design
• Flip-flop conversion

Excitation Table of SR, JK, D, T

Table 9: Excitation Tables of SR, JK, D and T Flip Flops

X means either 0 or 1 can be used.

Definition

PRESET and CLEAR are direct control inputs used to force the output into a known state.

They work without waiting for the clock. Therefore, they are called asynchronous inputs.

• PRESET forces Q = 1.
• CLEAR forces Q = 0.

Active-LOW Inputs

Active-LOW inputs are written as:

• ~PRE
• ~CLR

The input becomes active when its value is 0.

Fig. 6: JK Flip Flop with PRESET (S) and CLEAR (R) inputs

Table 10: Active-LOW PRESET and CLEAR Operation

 Benefits

• Starts a circuit from a known value.
• Clears counters and registers quickly.
• Initializes the circuit during power-up.
• Works even when the clock is stopped.
• Provides direct emergency control.

Conversion Method

One flip-flop can be made to behave like another by adding combinational logic to its inputs.

General method:

1. Write the truth table of the required flip-flop (inputs and present state).
2. Find the required next state Q(next) from input and present state.
3. Use the excitation table of the available flip-flop.
4. Find the required input equation.
5. Connect the logic circuit to the available flip-flop.

In this guide:

X to Y means implement Y behaviour using X flip-flop.

T to D Conversion

The required circuit must behave like a D flip-flop, but the available device is a T flip-flop.

Step 1: D Flip-Flop Behaviour

Q(next) = D

Step 2: T Flip-Flop Excitation

A T flip-flop:

• Holds when T = 0
• Toggles when T = 1

Table 11: D to T Conversion Table

Step 3: Input Equation

From the table:

T = D ⊕ Q

Step 4: Circuit

Connect D and the present output Q to an XOR gate. Connect the XOR output to the T input.

Fig. 7: Implementation of D Flip Flop using T Flip Flop

Other Flip-Flop Conversions

Table 12: Conversion Equations

CNT-Controlled D/T Using JK

Inputs: I, CNT.

Connections:

J = I
K = I ⊕ CNT

Fig. 8: Controlled D/T Flip Flop

Table 13: Controlled D/T Operation

• CNT = 0: The output holds or toggles according to I.
• CNT = 1: The output stores the value of I.

Structure

A JK master-slave flip-flop contains two connected stages:

1. Master latch
2. Slave latch

The master and slave operate during opposite clock levels.

Fig. 9: JK Master Slave Flip Flop Circuit

Working

• When CLK = 1, the master reads J and K.
• During this time, the slave remains disabled.
• When CLK changes to 0, the master becomes disabled.
• The slave reads the stored master output.
• The final output changes only once during one clock cycle.
• Input changes cannot directly reach the output while both stages are operating separately.

Table 14: JK Master-Slave Truth Table

Advantages

• Prevents race-around.
• Produces only one output change per clock cycle.
• Gives stable and predictable output.
• Separates input reading from output updating.

Disadvantages

• Uses more gates.
• Requires more circuit area.
• Has a larger propagation delay.
• Consumes more power than a simple latch.