Question.9
While both cnt and val map to 32-bit registers, what is the fundamental technical distinction between them when performing arithmetic in standard Verilog?
cnt
val
integer cnt; reg [31:0] val;
Select Answer
cnt is synthesizable, while val strictly serves as a testbench construct
cnt is natively interpreted as a signed value, whereas val operates strictly as unsigned by default
cnt cannot be manipulated using bitwise operators (&, |), while val can
&
|
cnt defaults to an initial simulation value of 0, whereas val defaults to x
0
x
