33. Data Types

Question.8

When compiling the above module, a synthesis error occurs. What is the fundamental root cause of this error regarding data types?

module flip_flop(
    input clk,
    input d,
    output q
);
    always @(posedge clk) begin
        q <= d;
    end
endmodule

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The always block must use blocking assignments (=) for q
The input clk must be declared as a reg to trigger the always block
The output q inherently defaults to a wire continuous net, but it is being illegally assigned procedurally inside an always block
The output q must be declared as an inout to retain its state across clock cycles

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