19. Modules

Question.4

Which Verilog module definition correctly implements the given RTL schematic?

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module top(input top_in, output top_out);
    modA u1;
    assign top_out = u1.w;
    assign u1.a = top_in;
endmodule

module top(input top_in, output top_out);
    assign top_out = modA(top_in);
endmodule

module top(input top_in, output top_out);
    modA(.a(top_in), .w(top_out));
endmodule

module top(input top_in, output top_out);
    wire intern;
    modA u1(.a(top_in), .w(intern));
    assign top_out = intern;
endmodule

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