19. Modules

Question.5

Why does this module fail to compile or synthesize correctly?

module toggle_ff(input clk, output q);
    always @(posedge clk) begin
        q <= ~q;
    end
endmodule

Need Help? Refer to the Quick Guide below

~ is an invalid operator inside procedural blocks.
Module outputs cannot be inverted in an assignment.
q defaults to a wire data type, which cannot be assigned in an always procedural block.
A continuous assign keyword is missing before q <= ~q.

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