19. Modules

Consider the following Verilog code:

module submodule (
    input a,
    input b,
    output c
);
    assign c = a & b;
endmodule

module top_module (
    input x,
    input y,
    output z
);
    // Instantiate submodule here:
    
endmodule

Which of the following instantiations correctly connects x to a, y to b, and z to c within the top_module?