19. Modules

Question.2

Which is the structurally correct syntax to define a Verilog module boundary?

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module my_design {
    input a;
    output b;
    assign b = a;
}

module my_design (
    input a,
    output b
);
    assign b = a;
endmodule

module my_design (
    input a,
    output b
);
    assign b = a;
end module

module my_design (
    input a,
    output b
);
    assign b = a;
    return;
endmodule

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