87. 4-bit Bidirectional Shift Register

How do you plan to solve it?

module shift_reg_bidirectional (
    input        CLK,
    input        RST,
    input        DIR,
    input        serial_in,
    output reg [3:0] Q
);
    // Write your code here
    always@(posedge CLK)begin
        if(RST)
          Q <= 4'd0;
        else begin
            case(DIR)
              1'b1 : Q <= {Q[2:0],serial_in};
              1'b0 : Q <= {serial_in,Q[3:1]};
              default : Q <= Q;
            endcase
        end
    end
    
endmodule