87. 4-bit Bidirectional Shift Register

How do you plan to solve it?

module shift_reg_bidirectional (
    input        CLK,
    input        RST,
    input        DIR,
    input        serial_in,
    output reg [3:0] Q
);
always @(posedge CLK or posedge RST)begin
    if(RST)
    Q<=0;

    else begin
        if(DIR)begin
            Q<={Q[2:0], serial_in};
        end
        else begin
        Q <= {serial_in, Q[3:1]};
        end
    end
end
        

    // Write your code here
    
endmodule