87. 4-bit Bidirectional Shift Register

How do you plan to solve it?

module shift_reg_bidirectional #(
    parameter NBITS = 4  // N-bits register
)(
    input                   CLK,
    input                   RST,
    input                   DIR,
    input                   serial_in,
    output reg [NBITS-1:0]  Q
);
    always @(posedge CLK or posedge RST) begin
        if (RST)      
            Q <= {NBITS{1'b0}};
        else begin
            if (DIR)
                Q <= {Q[NBITS-2 -: NBITS-1], serial_in};
            else
                Q <= {serial_in, Q[NBITS-1 -: NBITS-1]};
        end
    end
    
endmodule