87. 4-bit Bidirectional Shift Register

How do you plan to solve it?

module shift_reg_bidirectional (
    input        CLK,
    input        RST,
    input        DIR,
    input        serial_in,
    output reg [3:0] Q
);
  always@(posedge CLK or posedge RST) 
  begin
    if(RST==1)
    Q<=4'b0000;
    else if(DIR==1)
    Q<={Q[2:0],serial_in};
    else
    Q<={serial_in,Q[3:1]};// Write your code here
  end
endmodule